Visible to Intel only — GUID: GUID-13F11F2C-8857-4A8F-8BC6-314C01EFD208
Visible to Intel only — GUID: GUID-13F11F2C-8857-4A8F-8BC6-314C01EFD208
FPGA BSPs and Boards
As mentioned earlier in Types of SYCL* FPGA Compilation, generating an FPGA hardware image requires Quartus® Prime software, to map your design from RTL to the FPGA’s primitive hardware resources.
For BSPs necessary to compile to FPGA hardware, refer to the Intel® FPGA development flow webpage.
What is a Board?
Like a GPU, an FPGA is an integrated circuit that must be mounted onto a card or a board to interface with a server or a desktop computer. In addition to the FPGA, the board provides memory, power, and thermal management, and physical interfaces to allow the FPGA to communicate with other devices.
What is a BSP?
A BSP consists of software layers and an FPGA hardware scaffold design that makes it possible to target the FPGA through the Intel® oneAPI DPC++/C++ Compiler. The FPGA design generated by the compiler is stitched into the framework provided by the BSP.
Some BSPs are based on the Open FPGA Stack (OFS). OFS is an open-source hardware and software framework that provides reference shells called FPGA Interface Managers (FIM), upstreamed driver, management software tools and a oneAPI Accelerator Support Package (oneAPI ASP) for enabling oneAPI on custom platforms.
For more information about OFS, refer to https://ofs.github.io.
For more information about the oneAPI ASP, refer to oneAPI Accelerator Support Package (ASP): Getting Started User Guide and oneAPI Accelerator Support Package(ASP) Reference Manual: Open FPGA Stack.
What is Board Variant?
A BSP can provide multiple board variants that support different functionality. For example, a BSP could contain two variants that differ in their support for Unified Shared Memory (USM). For additional information about USM, refer to the Unified Shared Memory and USM Interfaces topics in the SYCL* Reference Documentation.
- Generating the FPGA Optimization Reports for your board requires a BSP. Contact your board provider for a BSP.
When running an executable on an FPGA board, you must ensure that you have initialized the FPGA board for the board variant that the executable is targeting. For information about initializing an FPGA board, refer to FPGA Board Initialization.
For information about FPGA optimizations possible with Restricted USM, refer to Prepinning Memory and Zero-Copy Memory Access.