Visible to Intel only — GUID: GUID-94C7862E-5B80-4E29-81E0-5AE33BEAAE8A
Visible to Intel only — GUID: GUID-94C7862E-5B80-4E29-81E0-5AE33BEAAE8A
cachesim-associativity
Set the cache associativity for modeling CPU cache behavior during Memory Access Patterns analysis.
GUI Equivalent
Project Properties > Analysis Target > Memory Access Patterns Analysis > Advanced > Cache associativity
Syntax
--cachesim-associativity=<integer> |
Arguments
<integer> is the number of cache locations where one memory entry can be placed: 1 | 2 | 4 | 8 | 16
Default
8
Actions Modified
collect=map --enable cache-simulation
Usage
1 stands for a direct mapped cache, where a memory entry can occupy only one cache line.
Cache simulation modeling applies to the following:
Memory Access Patterns analysis - This basic simulation functionality models accurate memory footprints, miss information, and cache line utilization for a downstream Memory Access Patterns report.
CPU / Memory Roofline Insights perspective - This enhanced simulation functionality models multiple levels of cache for a downstream Memory-Level Roofline chart or Roofline interactive HTML report.
This option is applicable only to Memory Access Patterns analysis.
Example
Run a Memory Access Patterns analysis. Model four-way associative cache with default cache line and cache set size.
advisor --collect=map --enable-cache-simulation --cachesim-associativity=4 --cachesim-mode=utilization --project-dir=./advi_results -- ./myApplication