Partial Reconfiguration
Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function. Create multiple personas for a particular region in your design without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA resources. PR enables the implementation of more complex FPGA systems.
Watch this video to learn more.
Application examples are shown in the simplified illustrations below. Figure A shows an application for algorithm acceleration, and Figure B shows a telecom application in optical networking. In both cases, the FPGA is reconfigured to implement different functions – a different algorithm in the case of algorithm acceleration, or a different client protocol in the telecom application (an optical networking muxponder). The key benefit here is that the rest of the FPGA continues to function.
Key Features
- Speed up in partial reconfiguration time for Intel® Stratix® 10 devices
- Push-button PR flow for faster time to market
- Compliments existing script-based flow
- Command line and graphical user interface for compilation and analysis
- Hierarchical partial reconfiguration that allows you to create child PR partitions in your design
- Simulation of partial reconfiguration that allows you to observe the resulting change and the intermediate effect in a reconfiguration partition
- Signal Tap logic analyzer debug with simultaneous acquisition of both the static region and partial reconfiguration regions
Quick Links
Application Notes
- AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel® Agilex® F-Series FPGA Development Board ›
- AN 987: Static Update Partial Reconfiguration Tutorial: for Intel® Agilex™ F-Series FPGA Development Board ›
- AN 964: Signal Tap Tutorial for Intel® Agilex™ Partial Reconfiguration Design ›
- AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel® Agilex® F-Series FPGA Development Board ›
- AN 953: Partially Reconfiguring a Design on Intel® Agilex® F-Series FPGA Development Board ›
- AN 826: hierarchical partial reconfiguration tutorial for Intel® Stratix® 10 GX FPGA development board ›
- AN 825: partially reconfiguring a design on Intel® Stratix® 10 GX FPGA development board ›
- AN 820: hierarchical partial reconfiguration over PCI express* reference design for Intel® Stratix® 10 devices ›
- AN 819: partial reconfiguration over PCI express* reference design for Intel® Stratix® 10 devices ›
- AN 818: static update partial reconfiguration tutorial for Intel® Stratix® 10 GX FPGA development board ›
- AN 817: static update partial reconfiguration tutorial for Intel® Arria® 10 GX FPGA development board ›
- AN 813: hierarchical partial reconfiguration over PCI express* reference design for Intel® Arria® 10 devices ›
- AN 806: hierarchical partial reconfiguration tutorial for Intel® Arria® 10 GX FPGA development board ›
- AN 797: partially reconfiguring a design on Intel® Arria® 10 GX FPGA development board ›
- AN 784: partial reconfiguration over PCI express* reference design for Intel® Arria® 10 devices ›
Online Training
- Partial reconfiguration for Intel® Arria® 10 devices: introduction & project assignments ›
- Partial reconfiguration for Intel® Arria® 10 devices: design guidelines & host requirements ›
- Partial reconfiguration for Intel® Arria® 10 devices: PR IP core & project flow ›
- Partial reconfiguration for Intel® Arria® 10 devices: output files & demonstration ›