Visible to Intel only — GUID: mwh1409960088177
Ixiasoft
Visible to Intel only — GUID: mwh1409960088177
Ixiasoft
2. Optimizing the Design Netlist
This chapter describes how you can use the Intel® Quartus® Prime Netlist Viewers to analyze and debug your designs.
As FPGA designs grow in size and complexity, the ability to analyze, debug, optimize, and constrain your design is critical. With today’s advanced designs, several design engineers are involved in coding and synthesizing different design blocks, making it difficult to analyze and debug the design. The Intel® Quartus® Prime RTL Viewer, State Machine Viewer, and Technology Map Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.
Section Content
When to Use the Netlist Viewers: Analyzing Design Problems
Intel Quartus Prime Design Flow with the Netlist Viewers
RTL Viewer Overview
State Machine Viewer Overview
Technology Map Viewer Overview
Netlist Viewer User Interface
Schematic View
State Machine Viewer
Cross-Probing to a Source Design File and Other Intel Quartus Prime Windows
Cross-Probing to the Netlist Viewers from Other Intel Quartus Prime Windows
Viewing a Timing Path
Optimizing the Design Netlist Revision History