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1.1. Intel FPGA Simulation Essential Elements
1.2. Overview of Simulation Tool Flow
1.3. Simulation Tool Flow
1.4. Supported Simulation Types
1.5. Supported Simulation Flows
1.6. Supported Hardware Description Languages
1.7. Supported Simulators
1.8. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition)
1.9. Intel FPGA Simulation Basics Revision History
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5.2. Aldec Active-HDL and Riviera-PRO Guidelines
The following guidelines apply to simulating Intel FPGA designs in the Active-HDL or Riviera-PRO software.
Compiling SystemVerilog Files
If your design includes multiple SystemVerilog files, you must compile the SystemVerilog files together with a single alog command.
If you have Verilog files and SystemVerilog files in your design, you must first compile the Verilog files, and then compile only the SystemVerilog files in the single alog command.