Transceiver Toolkit
Real-Time Transceiver Access for Faster Board Bring-Up
Transceiver Toolkit uses System Console technology to help FPGA and board designers validate transceiver link signal integrity in real-time in a system and improve board bring-up time. Test for bit-error rate (BER) while running multiple links at your target data rate to validate your board design with the Transceiver Toolkit. Tune transceiver analog settings for optimal link performance while using different test metrics to quantify results. Simultaneously test multiple devices across one or more boards using link tests in the Transceiver Toolkit GUI. Support for Agilex™ 5, Agilex™ 7, Stratix® 10, and Stratix® V FPGAs and includes adaptive equalization (AEQ) and decision feedback equalization (DFE) for signal transmission robustness. The latest additions include support for Agilex™ 5.
Transceiver Toolkit Features
- Offers FPGA and board designers real-time access to transceiver settings and improves board bring-up time.
- Provides bit-error rate test (BERT) function with pseudo-random binary sequence (PRBS) pattern generator and checker.
- Includes channel manager interface to monitor and track status while testing multiple channels simultaneously.
- Runs link tests between multiple devices across one or more boards.
- Determines the width and height of the signal eye with the Eye Viewer (available in selected devices).
- Offers access to signal integrity hardware features including AEQ and DFE.
- Provides the AutoSweep feature with a new interval-stepping capability that allows quick testing of many combinations of physical medium attachment (PMA) analog settings to find the optimal set for a particular transceiver link.
- Provides Eye Viewer integration with manual PMA setting controls and test plot management with save-and-load support that enables you to easily compare the signal integrity results.
- Provides new "AutoSweep & Eye Viewer" mode that allows automatic sweeping of PMA settings while capturing Eye Viewer data.
Table 1. Transceiver Toolkit Device Support
| Device Family | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Cyclone® V FPGAs and SoC FPGAs |
Cyclone® 10 FPGAs |
Arria® II GX FPGA |
Arria® V GX and GT FPGAs |
Arria® V GZ FPGA |
Arria® 10 FPGAs and SoC FPGAs |
Stratix® IV GX and GT FPGAs |
Stratix® V GX FPGA |
Stratix® V GT FPGA |
Stratix® 10 GX/SX/MX/TX SoC FPGAs |
Agilex™ 7 FPGAs |
Agilex™ 5 FPGAs | |
Real-time access |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
Built-in BERT function |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
Multichannel test |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
Multiple devices link test |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
Eye Viewer– signal eye width support |
- |
- |
- |
- |
✓ |
- |
✓ |
✓ |
✓ |
✓ |
✓ |
✓ |
Eye Viewer– signal eye height support |
- |
- |
- |
- |
✓ |
- |
- |
✓ |
✓ |
✓ |
✓ |
✓ |
AEQ |
- |
✓ |
- |
- |
✓ |
✓ |
- |
✓ |
- |
✓ |
✓ |
✓ |
DFE |
- |
- |
- |
- |
✓ |
✓ |
✓ |
✓ |
- |
✓ |
✓ |
✓ |
Getting Started:
- Agilex™ 5 FPGA GTS transceiver architecture and PMA and FEC direct PHY IP user guide ›
- Complete the transceiver toolkit training ›
- Quartus® Prime standard edition software and device support release notes ›
- Quartus® Prime pro edition software and device support release notes ›
- View transceiver toolkit reference designs ›
- Download the Quartus® Prime software ›
- GTS transceiver user guide ›