Platform Designer Tutorial Design Example

The Platform Designer (formerly Qsys) System Design Tutorial (PDF) guides you through the procedure of building a memory tester system in a top-down approach. It introduces new concepts of hierarchical isolation and generic components. It demonstrates new features like instantiating a generic component as a blackbox, checking system integrity and interface requirements, and synchronizing device settings and intellectual property (IP) references of the Intel® Quartus® Prime Pro Edition software and Platform Designer.

The design is scalable to test any Avalon® Memory Mapped (Avalon®-MM) slave interface capable of read-and-write accesses so you can use this design example as a starting point to test many other memory types and interfaces.

The Qsys System Design Tutorial - Standard Edition (PDF) provides step-by-step instructions to create and verify a design with the system integration tool in the Intel® Quartus® Prime software. This design example includes components to design a memory tester system. In the tutorial, you perform the following steps:

• Create a memory tester design using components in the system integration tool
• Build the design with hierarchical levels of subsystems
• Program the FPGA and calculate the memory efficiency reported by the tester
• Use bus functional models (BFMs) to validate one of the design components in simulation
• Use system console to control the system using a JTAG to the Avalon®-MM bridge

Software Requirements

This design requires the Intel® Quartus® Prime software, which includes:

• Nios® II Embedded Design Suite
• ModelSim*-Intel® FPGA or Starter Edition software

Download Intel® Quartus® Prime Standard Edition Software

Download Intel® Quartus® Prime Pro Edition Software

Using Design Examples

• Platform Designer Tutorial Design Example for Intel® Arria® 10 FPGA (.zip)
  • The ZIP file contains all the necessary hardware and software files to follow the procedures in the Platform Designer System Design Tutorial, along with a completed design. Design targets Intel® Arria® 10 GX FPGA Development Kit, with DDR4 SDRAM daughtercard installed. Design was tested in the Intel® Quartus® Prime Pro Edition software v17.0.
• Qsys Tutorial Design Example for Intel® Arria® 10 FPGA (.zip)
  • The ZIP file contains the completed design targeting Intel® Arria® 10 GX FPGA Development Kit, with DDR4 SDRAM daughtercard installed. Design was tested in the Intel® Quartus® Prime Standard Edition software v16.1.
• Qsys Tutorial Design Example (.zip)
  • The ZIP file contains all the necessary hardware and software files to follow the procedures in the Qsys System Design Tutorial and use the design example. Design targets the following development kits:
    • Nios® II Embedded Evaluation Kit (NEEK), Cyclone® III Edition
    • Arria® II GX FPGA Development Kit
    • Stratix® IV GX FPGA Development Kit
  • The README file included in this design provides instructions on how to port this design to your own custom board that meets the following board requirements:
    • Stratix, Cyclone, or Arria® series FPGA
      • 12K logic elements (LEs) or adaptive lookup tables (ALUTs) available
      • 128K memory bits available
    • JTAG programming cable connection
    • External memory to test and memory controller with the Avalon®-MM slave interface

The use of this design is governed by, and subject to, the terms and conditions of the Intel hardware reference design license agreement.

Block Diagram

Refer to the block diagram below for an overview of the design structure and the system components or cores included with the example.