I/O Management and Board Development Support Center

AN775: I/O Timing Information Generation Guidelines

I/O timing information is crucial for early analysis during PCB board design stages. Generate timing parameters to help you adjust the timing budget of your design, considering I/O standards and pin placement.

This chapter of the Intel Quartus Prime Pro Edition and Intel Quartus Prime Standard Edition Handbook discusses Intel FPGA I/O planning flow, detailing how and when to use the many I/O planning tools such as pin planner. It describes how to create top-level HDL files using pin planner's early I/O planning flow with custom megafunctions. It describes the methodology for I/O assignments and analysis, and discusses advanced I/O timing analysis with board trace models in Intel Quartus Prime Pro Edition and Intel Quartus Prime Standard Edition software.

This chapter of the Intel Quartus Prime Standard Edition Handbook explains how to use the SSN analyzer and optimization tool in Intel Quartus Prime Standard Edition software 9.0 and later. It discusses the tool flow and explains what is required to perform an accurate SSN analysis in your Intel FPGA design. It also describes Intel Quartus Prime Standard Edition software SSN optimization techniques and settings.

Using the Intel® Quartus® Prime Standard Edition Software: An Introduction

You will learn how to use Intel® Quartus® Prime Standard Edition software to develop an Intel FPGA design. You will create a new project, perform user settings and assignments, compile, simulate and configure your device to see the design working in-system.

• 80 Minute on-demand training course

In this training, learn about Interface Planner, formerly known as BluePrint, an easy-to-use tool in the Intel® Quartus® Prime Pro Edition software that uses the power of the Fitter to create a legal floorplan in minutes. Make guaranteed legal resource location assignments interface-by-interface instead of pin-by-pin to shorten your I/O planning cycle.

• 39 Minute on-demand training course

See a quick demonstration on Quartus II software's I/O assignment tools. You will learn how to use the Interface Planner features found in  Intel Quartus Prime Pro Edition software.

• 4 Minute demonstration

Describes support for optional third-party PCB design tools by Siemens EDA and Cadence*. Also includes information about signal integrity analysis and simulations with HSPICE and IBIS Models.

The Mentor Graphics* I/O Designer software allows you to take advantage of the full FPGA symbol design, creation, editing, and back-annotation flow supported by the Mentor Graphics* tools.

This chapter describes efficient planning and assignment of I/O pins in your target device. Consider I/O standards, pin placement rules, and your PCB characteristics early in the design phase.

This document contains a step-by-step tutorial and checklist of best-practice guidelines to design and review a power distribution network (PDN).

Includes information and suggestions for designing and laying out high-speed boards with Intel FPGAs.

Provides general information on high-speed board design.

Power Distribution Network (PDN) Tool

The easy-to-use power distribution network (PDN) design tool is a graphical tool used with all Intel® FPGAs to optimize the board-level PDN. The purpose of the board-level PDN is to distribute power and return currents from the voltage regulating module (VRM) to the FPGA power supplies, and support optimal transceiver signal integrity and FPGA performance.

With the ever-increasing operating speed of interfaces in traditional FPGA design, the timing and signal integrity margins between the FPGA and other devices on the board must be within specification and tolerance before building a PCB.

The Intel® Quartus® Prime software can export two different types of I/O models that are useful for different simulation situations, IBIS models and HSPICE models.

In this training, you will learn about the need for accurate signal integrity simulation & analysis when designing high-speed PCBs using Intel® FPGA transceivers. 

• 14 Minute on-demand training course