Verilog HDL Synthesis Attributes and Directives

altera_attribute

A Verilog HDL synthesis attribute that specifies the value of Quartus^® Prime options and assignments for Verilog HDL objects (modules, instances, nets, and registers).

chip_pin

A Verilog HDL synthesis attribute that assigns device pins to a port on a module.

direct_enable

A Verilog HDL synthesis attribute that guides Quartus^® Prime Integrated Synthesis as to which signals it should prefer as clock enable signals to the registers.

full_case

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to treat unspecified state values in a Verilog Design File Case Statement as don't care values, and therefore to treat the Case Statement as "full".

keep

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular net when optimizing combinational logic.

maxfan

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to duplicate a register to ensure that the register's fan-out does not exceed the maximum value you specify.

max_depth

A Verilog HDL synthesis attribute that specifies the maximum depth of the TriMatrix memory blocks used to implement an inferred RAM or ROM.

multstyle

A Verilog HDL synthesis attribute that specifies the type of implementation style for multiplication operations (*) in your HDL source.

noprune

A Verilog HDL synthesis attribute that prevents the Quartus^® Prime software from removing a register that does not directly or indirectly feed a top-level output or bidir pin.

parallel_case

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to implement parallel logic rather than a priority scheme for all case item expressions in a Verilog Design File Case Statement.

preserve

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to not minimize or remove a particular register when eliminating redundant registers or registers with constant drivers.

ram_init_file

A Verilog HDL synthesis attribute that specifies initial contents of an inferred memory.

ramstyle

A Verilog HDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred RAM.

romstyle

A Verilog HDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred ROM.

read_comments_as_HDL

A Verilog HDL synthesis directive that directs Analysis & Synthesis to perform logic synthesis on portions of the design code that are in comments.

syn_encoding

A Verilog HDL synthesis attribute that determines how the Quartus^® Prime software should encode the states of an inferred state machine.

translate_off translate_on

Verilog HDL synthesis directives that direct Analysis & Synthesis to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.

useioff

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to implement input, output, and output enable registers in I/O cells that have fast, direct connections to an I/O pin, when possible.

verilog_input_version

A Verilog HDL synthesis directive that specifies the Verilog HDL language version to use