full_case Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to treat unspecified state values in a Verilog Design File (.v) Definition Case Statement as don't care values. You can use this synthesis attribute on Case Statements that are not "full"— that is, Case Statements that do not contain all possible state values or a Default Statement—to prevent latch inferencing in the Case Statement.

To use the full_case synthesis attribute, you can specify the full_case synthesis attribute in a comment following the case, casex, or casez keyword and the case expression. In the comment, precede the synthesis attribute with the synthesis keyword.

For example, in the following code, the full_case synthesis attribute directs Analysis & Synthesis to treat the unspecified state value for 2'b11 as a don't care value:

module full_case (a, sel, y);
   input [3:0] a;
   input [1:0] sel;
   output y;
   reg y;
   always @(a or sel)           
      case (sel)      // synthesis full_case 
         2'b00: y=a[0];
         2'b01: y=a[1];
         2'b10: y=a[2];
      endcase
endmodule

Because unspecified state values act as latches during design simulation, the functionality you simulate for a design may be different from the functionality Analysis & Synthesis creates for the design using the full_case synthesis attribute. In the previous example, the Simulator treats the output for 2'b11 as a latch, while Analysis & Synthesis treats the output for 2'b11 as a don't care value. To avoid these differences in functionality when simulating and synthesizing a design, change the Case Statement so that it is "full".