multstyle Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that specifies the implementation style for multiplication operations (*) in your HDL source. Using this attribute, you can control whether the Quartus^® Prime software should preferentially implement a multiplication operation in general logic or dedicated hardware, if available in the target device.

Note: Analysis & Synthesis also recognizes the synonymous synthesis attribute syn_multstyle. This synthesis attribute behaves identically to the multstyle synthesis attribute.

To use the multstyle attribute in a Verilog Design File (.v) Definition, apply the attribute to a Module Declaration, a Variable Declaration, or a specific Binary Expression containing the * operator. The synthesis attribute must have a string value of "logic" or "dsp", indicating a preferred implementation in logic or in dedicated hardware, respectively.

Note: You can specify a multstyle of "dsp" for the Quartus^® Prime software to implement as multiplication in dedicated hardware if one operand is a constant and you are not multiplying by a power of 2. The final implementation depends on the availability of dedicated hardware in the target device.

When applied to a Module Declaration, the attribute specifies the default implementation style for all instances of the * operator in the module. For example, in the following code, the multstyle attribute directs the Quartus^® Prime software to implement all multiplications inside module foo in dedicated multiplication hardware.


(* multstyle = "dsp" *) module foo(...);           // Verilog 2001 attribute 
module foo(..) /* synthesis multstyle = "dsp" */;  // Embedded attribute

When applied to a Variable Declaration, the attribute specifies the implementation style to be used for a multiplication operator whose result is directly assigned to the variable. It overrides the multstyle attribute associated with the enclosing module, if present. For example, in the following code, the multstyle attribute attached to variable res directs the Quartus^® Prime software to implement the a * b in general logic rather than dedicated hardware.


wire [8:0] a, b;
(* multstyle = "logic" *) wire [17:0] res;              // Verilog 2001 attribute
// wire [17:0] res /* synthesis multstyle = "logic" */; // Embedded attribute
assign res = a * b;  // Multiplication must be directly assigned to res

When applied directly to a Binary Expression containing the * operator, the multstyle attribute specifies the implementation style for that specific operator alone and overrides any multstyle attribute associated with target variable or enclosing module. For example, in the following code, the multstyle attribute indicates that a * b should be implemented in dedicated hardware.


wire [8:0] a, b;
wire [17:0] res;
assign res = a * (* multstyle = "dsp" *) b;

Note: You must use the Verilog 2001 attribute syntax to apply the multstyle attribute to a Binary Expression.