syn_encoding Verilog HDL Synthesis Attribute
A Verilog HDL synthesis attribute that determines how the
Quartus® Prime software should encode the states of an inferred state
machine. Using the syn_encoding
attribute, you can control whether the state machine is safe and/or
user-encoded. Without the syn_encoding
attribute, the
Quartus® Prime software encodes the state machine
based on the State Machine
Processing logic option.
To use the syn_encoding
attribute in a Verilog Design File (.v) Definition,
apply the attribute to the declaration of your state variable. The
attribute takes a string value that consists of an encoding style,
such as "sequential" or
"one-hot". The
attribute can also take the value "safe", which
directs the
Quartus® Prime software to add extra logic to recover
from illegal states. The extra logic forces the state machine into
the reset state. You cannot specify manual recovery logic; the
Quartus® Prime software eliminates this logic while optimizing
your design.
You may combine the "safe" value
with an encoding style by separating the values with a comma, for
example, "safe,
one-hot".
(* syn_encoding = "user" *) reg [1:0] state; parameter init = 0, last = 3, next = 1, later = 2; always @ (state) begin case (state) init: out = 2'b01; next: out = 2'b10; later: out = 2'b11; last: out = 2'b00; endcase end
In the above example, the states will be encoded as follows:
init = "00" last = "11" next = "01" later = "10"
For convenience, the Quartus® Prime software accepts six encoding styles:
"default"— Choose an encoding based on the number of states in the enumeration type. If there are fewer than five states, use the"sequential"encoding. If there are more than five but fewer than 50 states, use a"one-hot"encoding. Otherwise, use a"gray"encoding."one-hot"— The default encoding style requiring N bits, where N is the number of states in the enumeration type."sequential"— Use a binary encoding in which the first state in the enumeration type has encoding 0, the second 1, and so on."gray"— Use an M-bit encoding in which the encodings for adjacent states differ by exactly one bit. An M-bit"gray"code can represent 2M states."johnson"—Use an M-bit encoding in which the encodings for adjacent states differ by exactly one bit. An M-bit"johnson"code can represent at most 2 times M states but requires less logic than a"gray"encoding."compact"— Use an encoding with fewest bits."user"— Encode each state using its value in the Verilog source. You can change the encoding of your state machine by changing the values of your state constants, .