read_comments_as_HDL Verilog HDL Synthesis Directive

A Verilog HDL synthesis directive that directs Analysis & Synthesis to perform logic synthesis on portions of the design code that are in comments. By commenting out code in the design and using this synthesis directive, you can direct Analysis & Synthesis to perform logic synthesis on code that is specific to logic synthesis, while also ensuring that the code does not affect design simulation.

To use the read_comments_as_HDL synthesis directive, you can specify the read_comments_as_HDL synthesis directive with the on keyword in a comment located immediately before the comments you want Analysis & Synthesis to process, and specify the read_comments_as_HDL synthesis directive with the off keyword in a comment located immediately after the comments you want Analysis & Synthesis to process. In the comment, precede the synthesis directive with the synthesis keyword.

For example, in the following code, Analysis & Synthesis performs logic synthesis on the comments // my_rom lpm_rom (.address (address), and // .data (data));. Analysis & Synthesis does not perform logic synthesis on any comments after the comment // synthesis read_comments_as_HDL off (unless the user uses the read_comments_as_HDL synthesis directive again).

// synthesis read_comments_as_HDL on
// // my_rom instantiation
// my_rom lpm_rom       (.address (address),
//                       .data      (data));
// synthesis read_comments_as_HDL off