translate_off and translate_on Verilog HDL Synthesis Directives
Verilog HDL synthesis directives that direct Analysis & Synthesis to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.
To use the translate_off and translate_on synthesis
directives, you can specify the translate_off synthesis directive in a
comment located immediately before the code you want Analysis & Synthesis to ignore,
and specify the translate_on synthesis directive in a comment located
immediately after the code you want Analysis & Synthesis to ignore. In the comment,
precede the synthesis directive with the synthesis keyword. The text
between the directives is treated as if each line is preceded by a single-line comment
delimiter. Syntax checking is not performed and there is no requirement that the text
be
valid Verilog HDL.
synthesis_off and synthesis_on. These synthesis
directives behave identically to the translate_off and
translate_on synthesis directives.
For example, in the following code, Analysis & Synthesis ignores the code
#tpd; and performs logic synthesis on any code after the comment
// synthesis translate_on (unless the user uses the
translate_off and translate_on synthesis directives
again):
parameter tpd = 2; // Generic delays// synthesis translate_off#tpd;// synthesis translate_onYou can use the Ignore translate_off and translate_on Synthesis
Directives logic option to disable all translate_off and
translate_on synthesis directives in a design, allowing you to use
the sections previously ignored during a compilation.