keep Verilog HDL Synthesis Attribute
A Verilog HDL synthesis attribute that directs Analysis & Synthesis to keep a particular wire intact. You can use this synthesis attribute to keep a combinational node so you can observe the node during simulation or with the Signal Tap Logic Analyzer.
syn_keep. This synthesis attribute behaves
identically to the keep synthesis attribute.
You cannot use this synthesis attribute for nodes that have no fan-out.
To use the keep synthesis attribute, you
can specify the keep synthesis attribute in a comment
that is on the same line as the combinational node you want Analysis & Synthesis to
keep. In the comment, precede the synthesis attribute with the synthesis keyword.
For example, in the following code, the comment /* synthesis keep */ directs Analysis & Synthesis to not minimize the
keep_wire combinational node:
wire keep_wire /* synthesis keep */;