noprune Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that prevents the Quartus^® Prime software from removing a register that does not directly or indirectly feed a top-level output or bidir pin, such as a fan-out free register. This attribute differs from the preserve attribute, which prevents a register from being reduced to a constant or merged with a duplicate register. Standard synthesis optimizations remove nodes that do not directly or indirectly feed a top-level output pin or bidir pin.

You may wish to retain a fan-out free register in many cases, for example, if you are compiling a preliminary design that will eventually include fan-out logic for the register. You may also intend to use the register for debugging in the Signal Tap Logic Analyzer. Finally, you may want to route from the register to a Signal Probe Pin after compilation.

Internally, the Quartus^® Prime software implements a noprune attribute using the Preserve Fan-out Free Register Node logic option. For information about device support for the noprune attribute, see the Preserve Fan-out Free Register Node logic option.

You can use Verilog 2001 attribute syntax to preserve a fanout-free register, as shown in the following code:

(* noprune *) reg reg1;

You can also embed the attribute in a block comment that follows the register's variable declaration.

For example, in the following code, the comment /* synthesis noprune */ directs Analysis & Synthesis to preserve the fanout-free register reg1:

reg reg1 /* synthesis noprune */;