romstyle Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred ROM Definition in your design. The Quartus^® Prime software supports this synthesis attribute only for device families that support the TriMatrix Memory architecture.

To use the romstyle attribute in a Verilog Design File (.v) Definition, specify the synthesis attribute in a comment following the Variable Declaration of an inferred ROM whose implementation you want to control. In the comment, precede the synthesis attribute with the synthesis keyword. In addition, the synthesis attribute value must be a string value of "logic", "M4K","M9K", "M144K", or "MLAB", depending on the type of memory block you want the Quartus^® Prime software to use when implementing the inferred ROM. If you use the synthesis attribute on anything except a variable that represents a ROM, or if you specify an illegal value, the Quartus^® Primesoftware ignores that synthesis attribute.

For example, in the following code, the romstyle synthesis attribute specifies that you use an M9K memory block Definitionto infer the ROM my_rom:

(* romstyle = "M9K" *) output reg [7:0] q; 
  reg [4:0] addr_reg; 
  always@(posedge clk) begin 
    addr_reg <= addr; 
    case(addr_reg) 
      0: q <= 8'h01; 
      1: q <= 8'h02; 
      2: q <= 8'h03; 
      3: q <= 8'h04; 
      4: q <= 8'h05; 
      5: q <= 8'h06; 
      6: q <= 8'h07;
      ...
      endcase 
  end