ram_init_file Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that specifies initial contents of an inferred memory block in the form of a Memory Initialization File (.mif) Definition. The attribute takes a string value containing the name of the RAM Initialization File (.rif).

Note: Analysis & Synthesis also recognizes the synonymous synthesis attribute syn_ram_init_file, which behaves identically to the ram_init_file synthesis attribute.

To use the ram_init_file attribute in a Verilog Design File (.v) Definition specify the synthesis attribute delimited by (* and *) preceding the Variable Declaration of an inferred RAM, whose implementation you want to control.

For example, in the following code, the ram_init_file synthesis attribute specifies that the inferred RAM mem should be initialized with the content specified in my_init_file.mif :

(* ram_init_file = "my_init_file.mif" *) reg [7:0] mem[0:255];

Note: You can also specify the synthesis attribute of an inferred RAM, whose implementation you want to control, in a comment following the Variable Declaration. In the comment, the synthesis keyword must precede the synthesis attribute, as shown in the following code:

reg [7:0] mem[0:255] /* synthesis ram_init_file = " my_init_file.mif" */;