verilog_input_version Synthesis Directive

A Verilog HDL synthesis directive that specifies the Verilog HDL language version to use inside a Verilog Design File (.v) DefinitionorSystemVerilog Design File (.sv) Definition. This directive overrides the default HDL version and any HDL version specified in the File Properties dialog box.


// synthesis VERILOG_INPUT_VERSION <language version>

To use the VERILOG_INPUT_VERSION directive, embed it in a Verilog HDL comment at the point where you want to start using that language version. This directive takes a single string argument, the <language version> of the Verilog HDL language you wish to use, which can be VERILOG_1995, VERILOG_2001, or SYSTEMVERILOG_2005.

Note: You cannot change Verilog HDL language versions in the middle of a design unit.

When the Quartus^® Prime software reads a VERILOG_INPUT_VERSION directive, it changes the current language version as specified until the end of the file, or until it reaches the next VERILOG_INPUT_VERSION directive.