parallel_case Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that directs Analysis & Synthesis to implement parallel logic rather than a priority scheme for all case item expressions in a Verilog Design File (.v) Definition Case Statement. You can use this synthesis attribute on Case Statements that do not contain mutually exclusive case item expressions to ensure that overlapping case items can be executed at the same time.

To use the parallel_case synthesis attribute, you can specify the parallel_case synthesis attribute in a comment following the case, casex, or casez keyword and the case expression. In the comment, precede the synthesis attribute with the synthesis keyword.

For example, in the following code, the parallel_case synthesis attribute directs Analysis & Synthesis to implement parallel logic on the 3'b1??, 3'b?1?, and 3'b??1 case items expressions:

module parallel_case (sel, a, b, c);
   input [2:0] sel;
   output a, b, c;
   reg a, b, c;
   always @(sel)                
   begin
      {a, b, c} = 3'b0;
      casez (sel)                // synthesis parallel_case 
         3'b1??: a = 1'b1;
         3'b?1?: b = 1'b1;
         3'b??1: c = 1'b1;
      endcase
   end
endmodule

Because the case item expressions are implemented with a priority scheme during design simulation, the functionality you simulate for a design may be different from the functionality Analysis & Synthesis creates for the design using the parallel_case synthesis attribute. In the previous example, the Simulator implements a priority scheme for the case item expressions where the bits of the input sel have a high-to-low priority order of sel[2], sel[1], and sel[0], while Analysis & Synthesis implements parallel logic where all the bits of sel have equal priority.