chip_pin Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that assigns device pins to a port on a module.

To use the chip_pin synthesis attribute in a Verilog Design File (.v) Definition, specify the synthesis attribute in between (* and *) delimiters in the same line as the Port Declaration for the input or output port to which you are assigning pins. The synthesis attribute value must be a string containing a list of device pin names separated by commas (,).

Note:

You can also specify the synthesis attribute in a comment located in the same line as the Port Declaration for the input or output port to which you are assigning pins. In the comment, precede the synthesis attribute with the synthesis keyword and any device pin names should be separated by commas.
In addition to the chip_pin attribute, the Quartus^® Prime software supports the altera_chip_pin_lc attribute for compatibility with third-party synthesis tools. Some of these synthesis tools required an @ symbol in front of each pin name when targeting some older device families. In the Quartus^® Prime software, the @ symbol is optional.
To find the name for each pin you want to assign to a port, consult the pin table for the design's target device.
The chip_pin synthesis attribute can be used only on the ports of the top-level entity in the design, and cannot be used to assign pin locations from entities at lower levels of the design hierarchy.

You can use the chip_pin synthesis attribute only on module ports with single-bit or one-dimensional types. For one-dimensional ports, the port's range declaration determines the mapping of pins listed in the synthesis attribute to individual bits in the port. For example, in the following code, the chip_pin synthesis attribute assigns device pins to ports sel and data on module foo:


// Verilog-2001 attribute syntax module foo(sel, data, o);
    (* chip_pin = "C4" *) input sel;
    (* chip_pin = "D1, D2, D3, D4" *) input [3:0] data;
    output o;
        // Specify module body
         
endmodule // Traditional comment-style syntax
module foo(sel, data, o);
  
   input sel /* synthesis chip_pin = "C4" */;
   input [3:0] data; /* synthesis chip_pin = "D1, D2, D3, D4" */;
   output o;
       // Specify module body
       
endmodule

In this example, sel is a one bit wide port; pin C4 is assigned to this port. data is a one-dimensional port that is four bits wide. Because data is declared as input [3:0] data, pin D1 is assigned to data[3], pin D2 is assigned to data[2], and so forth. If you declared data as input [0:3] data, pin D1 would be assigned to data[0], pin D2 would assigned to data[1], and so forth.

Note: The number of entries in the synthesis attribute's comma-delimited list must match the number of bits in the port. To leave a specific bit in a one-dimensional port unassigned, leave its corresponding pin assignment blank.

You cannot use the chip_pin synthesis attribute to make pin assignments on instance ports, or module ports with more than two dimensions, such as memories.