useioff Verilog HDL Synthesis Attribute

A VerilogHDL synthesis attribute that directs the Quartus^® Prime software to implement input, output, and output enable registers in I/O cells that have fast, direct connections to an I/O pin, when possible. Using this option can improve I/O cell performance by minimizing setup, clock-to-output, and clock-to-output enable times.

To use the useioff synthesis attribute, specify the useioff synthesis attribute in between (* and *) delimiters. In addition, the synthesis attribute value must be 1 or 0. Specifying the useioff synthesis attribute to 1 directs the Quartus^® Prime software to pack registers into the I/O cells representing the port. Specifying the useioff synthesis attribute to 0 prevents register packing into the I/O cells.

You can also embed the useioff attribute in comments preceded by the synthesis keyword.

For example, in the following code, the useioff synthesis attribute directs the Quartus^® Prime software to implement the registers a_reg, b_reg, and o_reg in the I/O cells corresponding to the ports a, b, and o, respectively:

// Verilog-2001 attribute syntax module top_level(clk, a, b, o);
   input clk;
   (* useioff = 1 *) input [1:0] a, b;
   (* useioff = 1 *) output [2:0] o;
   reg [1:0] a_reg, b_reg;
   reg [2:0] o_reg;
   always@(posedge clk) 
   begin
      a_reg <= a;
      b_reg <= b;
      o_reg <= a_reg + b_reg;
   end    
   assign o = o_reg;
endmodule \\Traditional comment-style syntaxmodule top_level(clk, a, b, o);
    input clk;
    input [1:0] a, b /* synthesis useioff = 1 */;
    output [2:0] o /* synthesis useioff = 1 */;
    reg [1:0] a_reg, b_reg;    reg [2:0] o_reg;
    always@(posedge clk)
    begin
       a_reg <= a;
       b_reg <= b;
       o_reg <= a_reg + b_reg;
    end    assign o = o_reg; endmodule