preserve Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that prevents Analysis & Synthesis from minimizing or removing a particular register. You can use this synthesis attribute to preserve a register for later observation with the Quartus^® Prime Simulator or the Signal Tap Logic Analyzer. You can also use this synthesis attribute to prevent register optimizations to a preliminary version of your design. For example, if a register's input is a constant VCC, Analysis & Synthesis may use the Power-Up Don't Care logic option to minimize the register away completely. By setting the preserve synthesis attribute on the register, you can prevent this optimization.

The preserve synthesis attribute does not prevent register duplication or register packing optimizations from occurring. Duplication and register packing optimizations are reported in the Analysis & Synthesis Netlist Optimizations report and the Fitter Netlist Optimizations report when they occur. To prevent all optimizations to a register, see the help documentation on the Netlist Optimizations logic option.

There are two important limitations of the preserve synthesis attribute:

• It prevents a register from being inferred as a state machine.
• It does not preserve fanout-free registers. Use the noprune synthesis attribute to prevent Analysis & Synthesis from removing fanout-free registers.

You can use Verilog 2001 attribute syntax to preserve a register, as shown in the following code:

(*preserve*) reg reg1;

You can also embed the attribute in a block comment that follows the variable declaration for the register you wish to preserve. You can also set the attribute on a module, which directs Analysis & Synthesis to preserve all registers in the module, except for those registers that infer state machines.

For example, in the following code, the comment /* synthesis preserve */ directs Analysis & Synthesis to preserve the reg1 register:

reg reg1 /* synthesis preserve */;