ic_con |
0x0 |
32 |
RW |
0x7D |
Control Register |
ic_tar |
0x4 |
32 |
RW |
0x1055 |
Target Address Register |
ic_sar |
0x8 |
32 |
RW |
0x55 |
Slave Address Register |
ic_data_cmd |
0x10 |
32 |
RW |
0x0 |
Tx Rx Data and Command Register |
ic_ss_scl_hcnt |
0x14 |
32 |
RW |
0x190 |
Std Spd Clock SCL HCNT Register |
ic_ss_scl_lcnt |
0x18 |
32 |
RW |
0x1D6 |
Std Spd Clock SCL LCNT Register |
ic_fs_scl_hcnt |
0x1C |
32 |
RW |
0x3C |
Fast Spd Clock SCL HCNT Register |
ic_fs_scl_lcnt |
0x20 |
32 |
RW |
0x82 |
Fast Spd Clock SCL LCNT Register |
ic_intr_stat |
0x2C |
32 |
RO |
0x0 |
Interrupt Status Register |
ic_intr_mask |
0x30 |
32 |
RW |
0x8FF |
Interrupt Mask Register |
ic_raw_intr_stat |
0x34 |
32 |
RO |
0x0 |
Raw Interrupt Status Register |
ic_rx_tl |
0x38 |
32 |
RW |
0x0 |
Receive FIFO Threshold Register |
ic_tx_tl |
0x3C |
32 |
RW |
0x0 |
Transmit FIFO Threshold Level Register |
ic_clr_intr |
0x40 |
32 |
RO |
0x0 |
Combined and Individual Interrupt Register |
ic_clr_rx_under |
0x44 |
32 |
RO |
0x0 |
Rx Under Interrupt Register |
ic_clr_rx_over |
0x48 |
32 |
RO |
0x0 |
RX Over Interrupt Register |
ic_clr_tx_over |
0x4C |
32 |
RO |
0x0 |
TX Over Interrupt Register |
ic_clr_rd_req |
0x50 |
32 |
RO |
0x0 |
Interrupt Read Request Register |
ic_clr_tx_abrt |
0x54 |
32 |
RO |
0x0 |
Tx Abort Interrupt Register |
ic_clr_rx_done |
0x58 |
32 |
RO |
0x0 |
Rx Done Interrupt Register |
ic_clr_activity |
0x5C |
32 |
RO |
0x0 |
Activity Interrupt Register |
ic_clr_stop_det |
0x60 |
32 |
RO |
0x0 |
Stop Detect Interrupt Register |
ic_clr_start_det |
0x64 |
32 |
RO |
0x0 |
Start Detect Interrupt Register |
ic_clr_gen_call |
0x68 |
32 |
RO |
0x0 |
GEN CALL Interrupt Register |
ic_enable |
0x6C |
32 |
RW |
0x0 |
Enable Register |
ic_status |
0x70 |
32 |
RO |
0x6 |
Status Register |
ic_txflr |
0x74 |
32 |
RO |
0x0 |
Transmit FIFO Level Register |
ic_rxflr |
0x78 |
32 |
RO |
0x0 |
Receive FIFO Level Register |
ic_sda_hold |
0x7C |
32 |
RW |
0x1 |
SDA Hold Register |
ic_tx_abrt_source |
0x80 |
32 |
RW |
0x0 |
Transmit Abort Source Register |
ic_slv_data_nack_only |
0x84 |
32 |
RW |
0x0 |
Generate Slave Data NACK |
ic_dma_cr |
0x88 |
32 |
RW |
0x0 |
DMA Control |
ic_dma_tdlr |
0x8C |
32 |
RW |
0x0 |
DMA Transmit Data Level |
ic_dma_rdlr |
0x90 |
32 |
RW |
0x0 |
Receive Data Level |
ic_sda_setup |
0x94 |
32 |
RW |
0x64 |
SDA Setup Register |
ic_ack_general_call |
0x98 |
32 |
RW |
0x1 |
ACK General Call |
ic_enable_status |
0x9C |
32 |
RO |
0x0 |
Enable Status Register |
ic_fs_spklen |
0xA0 |
32 |
RW |
0x2 |
SS and FS Spike Suppression Limit Register |
ic_comp_param_1 |
0xF4 |
32 |
RO |
0x3F3FEA |
Component Parameter Register 1 |
ic_comp_version |
0xF8 |
32 |
RO |
0x3132302A |
Component Version Register |
ic_comp_type |
0xFC |
32 |
RO |
0x44570140 |
Component Type Register |