ic_ss_scl_lcnt

This register sets the SCL clock low-period count for standard speed

Module Instance	Base Address	Register Address
`i2c0`	`0xFFC04000`	`0xFFC04018`
`i2c1`	`0xFFC05000`	`0xFFC05018`
`i2c2`	`0xFFC06000`	`0xFFC06018`
`i2c3`	`0xFFC07000`	`0xFFC07018`

Offset: 0x18

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ic_ss_scl_lcnt` `RW 0x1D6`

ic_ss_scl_lcnt Fields

Bit	Name	Description	Access	Reset
15:0	`ic_ss_scl_lcnt`	This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This field sets the SCL clock low period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the Enable Register register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this from being written, and if attempted, results in 8 being set.	`RW`	`0x1D6`