ic_fs_scl_hcnt
This register sets the SCL clock high-period count for fast speed
| Module Instance | Base Address | Register Address |
|---|---|---|
| i2c0 | 0xFFC04000 | 0xFFC0401C |
| i2c1 | 0xFFC05000 | 0xFFC0501C |
| i2c2 | 0xFFC06000 | 0xFFC0601C |
| i2c3 | 0xFFC07000 | 0xFFC0701C |
Offset: 0x1C
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ic_fs_scl_hcnt RW 0x3C |
|||||||||||||||
ic_fs_scl_hcnt Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 15:0 | ic_fs_scl_hcnt | This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register goes away and becomes read-only returning 0s if in Standard Speed Mode. This register can be written only when the I2C interface is disabled, which corresponds to the Enable Register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this from being written, and if attempted results in 6 being set. |
RW | 0x3C |