ic_enable_status

This register is used to report the i2c hardware status when the IC_ENABLE register is set from 1 to 0; that is, when i2c is disabled. If IC_ENABLE has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE has been set to 0, bits 2:1 are only valid as soon as bit 0 is read as '0'. Note: When ic_enable has been written with '0' a delay occurs for bit 0 to be read as '0' because disabling the i2c depends on I2C bus activities.

Module Instance	Base Address	Register Address
`i2c0`	`0xFFC04000`	`0xFFC0409C`
`i2c1`	`0xFFC05000`	`0xFFC0509C`
`i2c2`	`0xFFC06000`	`0xFFC0609C`
`i2c3`	`0xFFC07000`	`0xFFC0709C`

Offset: 0x9C

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`													`slv_rx_data_lost` `RO 0x0`	`slv_disabled_while_busy` `RO 0x0`	`ic_en` `RO 0x0`

ic_enable_status Fields

Bit	Name	Description	Access	Reset
2	`slv_rx_data_lost`	This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC ENABLE from 1 to 0. When read as 1, i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the i2c has a chance to NACK a transfer, and ic_enable has been set to 0, then this bit is also set to 1. When read as 0, i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.	`RO`	`0x0`
1	`slv_disabled_while_busy`	This bit indicates if a potential or active Slave operation has been aborted due to the setting of the ic_enable register from 1 to 0. This bit is set when the CPU writes a 0 to the ic_enable register while: (a) I2C is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, I2C is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the i2c has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as 0, i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.	`RO`	`0x0`
0	`ic_en`	This bit always reflects the value driven on the output port ic_en. Not used in current application. When read as 1, i2c is deemed to be in an enabled state. When read as 0, i2c is deemed completely inactive. NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read slv_rx_data_lost (bit 2) and slv_disabled_while_busy (bit 1).	`RO`	`0x0`