ic_fs_spklen

This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS or FS modes.

Module Instance	Base Address	Register Address
`i2c0`	`0xFFC04000`	`0xFFC040A0`
`i2c1`	`0xFFC05000`	`0xFFC050A0`
`i2c2`	`0xFFC06000`	`0xFFC060A0`
`i2c3`	`0xFFC07000`	`0xFFC070A0`

Offset: 0xA0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`spklen` `RW 0x2`

ic_fs_spklen Fields

Bit	Name	Description	Access	Reset
7:0	`spklen`	This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 2 being set.	`RW`	`0x2`