ic_clr_tx_abrt

Clear TX_ABRT Interrupt

Module Instance	Base Address	Register Address
`i2c0`	`0xFFC04000`	`0xFFC04054`
`i2c1`	`0xFFC05000`	`0xFFC05054`
`i2c2`	`0xFFC06000`	`0xFFC06054`
`i2c3`	`0xFFC07000`	`0xFFC07054`

Offset: 0x54

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`clr_tx_abort` `RO 0x0`

ic_clr_tx_abrt Fields

Bit	Name	Description	Access	Reset
0	`clr_tx_abort`	Read this register to clear the TX_ABRT interrupt (bit 6) of the ic_raw_intr_stat register, and the ic_tx_abrt_source register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the ic_tx_abrt_source register for an exception to clearing ic_tx_abrt_source.	`RO`	`0x0`