ic_status
This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.When the I2C is disabled by writing 0 in bit 0 of the ic_enable register:
- Bits 1 and 2 are set to 1
- Bits 3 and 4 are set to 0
When the master or slave state machines goes to idle
- Bits 5 and 6 are set to 0
Module Instance | Base Address | Register Address |
---|---|---|
i2c0 | 0xFFC04000 | 0xFFC04070 |
i2c1 | 0xFFC05000 | 0xFFC05070 |
i2c2 | 0xFFC06000 | 0xFFC06070 |
i2c3 | 0xFFC07000 | 0xFFC07070 |
Offset: 0x70
Access: RO
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
slv_activity RO 0x0 |
mst_activity RO 0x0 |
rff RO 0x0 |
rfne RO 0x0 |
tfe RO 0x1 |
tfnf RO 0x1 |
activity RO 0x0 |
ic_status Fields
Bit | Name | Description | Access | Reset | ||||||
---|---|---|---|---|---|---|---|---|---|---|
6 | slv_activity | Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set.
|
RO | 0x0 | ||||||
5 | mst_activity | When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. Note:IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.
|
RO | 0x0 | ||||||
4 | rff | Receive FIFO Completely Full.
|
RO | 0x0 | ||||||
3 | rfne | Receive FIFO Not Empty.
|
RO | 0x0 | ||||||
2 | tfe | Transmit FIFO Empty.
|
RO | 0x1 | ||||||
1 | tfnf | Transmit Fifo Full
|
RO | 0x1 | ||||||
0 | activity | I2C Activity. |
RO | 0x0 |