ic_data_cmd

This bit controls whether a RESTART is issued before the byte is sent or received. 1 = A RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command. 0 = A RESTART is issued only if the transfer direction is changing from the previous command.

This bit controls whether a STOP is issued after the byte is sent or received. 1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. 0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO.

This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the CPU data is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a tx_abrt interrupt (bit 6 of the Raw Intr Status Register), unless bit 11 special in the Target Address Register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a tx_abrt interrupt occurs. NOTE: It is possible that while attempting a master I2C read transfer on I2C, a RD_REQ interrupt may have occurred simultaneously due to a remote I2C master addressing I2C. In this type of scenario, I2C ignores the Data Cmd write, generates a tx_abrt interrupt, and waits to service the RD_REQ interrupt.

This Field contains the data to be transmitted or received on the I2C bus. If you are writing to these bits and want to perform a read, bits 7:0 (dat) are ignored by the I2C. However, when you read from this register, these bits return the value of data received on the I2C interface.