ic_ss_scl_hcnt
This register sets the SCL clock high-period count for standard speed.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i2c0 | 0xFFC04000 | 0xFFC04014 |
| i2c1 | 0xFFC05000 | 0xFFC05014 |
| i2c2 | 0xFFC06000 | 0xFFC06014 |
| i2c3 | 0xFFC07000 | 0xFFC07014 |
Offset: 0x14
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ic_ss_scl_hcnt RW 0x190 |
|||||||||||||||
ic_ss_scl_hcnt Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 15:0 | ic_ss_scl_hcnt | This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This field sets the SCL clock high-period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the Enable Register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. It is readable and writeable. NOTE: This register must not be programmed to a value higher than 65525, because I2C uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. |
RW | 0x190 |