ic_intr_stat

Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling I2C or when the CPU reads bit 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx buffer.

Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode.

Indicates whether a STOP condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode.

This bit captures I2C activity and stays set until it is cleared. There are four ways to clear it: - Disabling the I2C - Reading the ic_clr_activity register - Reading the ic_clr_intr register - I2C reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the I2C module is idle, this bit remains set until cleared, indicating that there was activity on the bus.

When the I2C is acting as a slave-transmitter, this bit is set to 1, if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.

This bit indicates if I2C, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'.When this bit is set to 1, the ic_tx_abrt_source register indicates the reason why the transmit abort takes places. NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface.

This bit is set to 1 when i2c is acting as a slave and another I2C master is attempting to read data from I2C. The I2C holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the ic_clr_rd_req register.

This bit is set to 1 when the transmit buffer is at or below the threshold value set in the ic_tx_tl register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, this bit is set to 0.

Set during transmit if the transmit buffer is filled to 64 and the processor attempts to issue another I2C command by writing to the Data and Command Register. When the module is disabled, this bit keeps its level until the master or slave state machines goes into idle, then interrupt is cleared.

Set when the receive buffer reaches or goes above the Receive FIFO Threshold Value(rx_tl). It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled, Bit [0] of the Enable Register set to 0, the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the Enable Register Bit 0 is programmed with a 0, regardless of the activity that continues.

Set if the receive buffer is completely filled to 64 and an additional byte is received from an external I2C device. The I2C acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled, Enable Register bit[0] is set to 0 this bit keeps its level until the master or slave state machines go into idle, then this interrupt is cleared.

Set if the processor attempts to read the receive buffer when it is empty by reading from the Tx Rx Data and Command Register. If the module is disabled, Enable Register is set to 0, this bit keeps its level until the master or slave state machines go into idle, then this interrupt is cleared.