ic_tar

This register can be written to only when the ic_enable register is set to 0. This register is 13 bits wide. All bits can be dynamically updated as long as any set of the following conditions are true, (Enable Register bit 0 is set to 0) or (Enable Register bit 0 is set to 1 AND (I2C is NOT engaged in any Master [tx, rx] operation [ic_status register mst_activity bit 5 is set to 0]) AND (I2C is enabled to operate in Master mode[ic_con bit[0] is set to one]) AND (there are NO entries in the TX FIFO Register [IC_STATUS bit [2] is set to 1])
Module Instance Base Address Register Address
i2c0 0xFFC04000 0xFFC04004
i2c1 0xFFC05000 0xFFC05004
i2c2 0xFFC06000 0xFFC06004
i2c3 0xFFC07000 0xFFC07004

Offset: 0x4

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ic_10bitaddr_master

RW 0x1

special

RW 0x0

gc_or_start

RW 0x0

ic_tar

RW 0x55

ic_tar Fields

Bit Name Description Access Reset
12 ic_10bitaddr_master

This bit controls whether the i2c starts its transfers in 7-bit or 10-bit addressing mode when acting as a master.

Value Description
0x0 Master Address, 7bit
0x1 Master Address, 10bit
RW 0x1
11 special

This bit indicates whether software performs a General Call or START BYTE command.

Value Description
0x0 Ignore bit 10 gc_or_start and use ic_tar normally
0x1 Perform special I2C command as specified in gc_or_start
RW 0x0
10 gc_or_start

If bit 11 (SPECIAL) of this Register is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the I2C or General Call Address after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the Raw Interrupt_Status register. The I2C remains in General Call mode until the special bit value (bit 11) is cleared.

Value Description
0x0 General Call
0x1 START Byte
RW 0x0
9:0 ic_tar

This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the ic_tar and ic_sar are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.

 RW 0x55