ic_clr_tx_over
Clears Over Interrupts
| Module Instance | Base Address | Register Address |
|---|---|---|
| i2c0 | 0xFFC04000 | 0xFFC0404C |
| i2c1 | 0xFFC05000 | 0xFFC0504C |
| i2c2 | 0xFFC06000 | 0xFFC0604C |
| i2c3 | 0xFFC07000 | 0xFFC0704C |
Offset: 0x4C
Access: RO
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
clr_tx_over RO 0x0 |
||||||||||||||
ic_clr_tx_over Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 0 | clr_tx_over | Read this register to clear the TX_OVER interrupt (bit 3) of the ic_raw_intr_stat register. |
RO | 0x0 |