ic_rxflr

This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in ic_tx_abrt_source The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.

Module Instance	Base Address	Register Address
`i2c0`	`0xFFC04000`	`0xFFC04078`
`i2c1`	`0xFFC05000`	`0xFFC05078`
`i2c2`	`0xFFC06000`	`0xFFC06078`
`i2c3`	`0xFFC07000`	`0xFFC07078`

Offset: 0x78

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`									`rxflr` `RO 0x0`

ic_rxflr Fields

Bit	Name	Description	Access	Reset
6:0	`rxflr`	Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.	`RO`	`0x0`