ic_sda_hold
This register controls the amount of time delay (in terms of number of l4_sp_clk clock periods) introduced in the falling edge of SCL, relative to SDA changing, when I2C services a read request in a slave-transmitter operation. The relevant I2C requirement is thd:DAT as detailed in the I2C Bus Specification.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i2c0 | 0xFFC04000 | 0xFFC0407C |
| i2c1 | 0xFFC05000 | 0xFFC0507C |
| i2c2 | 0xFFC06000 | 0xFFC0607C |
| i2c3 | 0xFFC07000 | 0xFFC0707C |
Offset: 0x7C
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ic_sda_hold RW 0x1 |
|||||||||||||||
ic_sda_hold Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 15:0 | ic_sda_hold | Program to a minimum 0f 300ns. |
RW | 0x1 |