ic_dma_rdlr

DMA Control Signals Interface.

Module Instance	Base Address	Register Address
`i2c0`	`0xFFC04000`	`0xFFC04090`
`i2c1`	`0xFFC05000`	`0xFFC05090`
`i2c2`	`0xFFC06000`	`0xFFC06090`
`i2c3`	`0xFFC07000`	`0xFFC07090`

Offset: 0x90

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`										`dmardl` `RW 0x0`

ic_dma_rdlr Fields

Bit	Name	Description	Access	Reset
5:0	`dmardl`	This bit field controls the level at which a DMA request is made by the receive logic. The watermark level \= DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when or more data entries are present in the receive FIFO.	`RW`	`0x0`