System Manager Module Summary

Registers in the System Manager module

Base Address: 0xFFD08000

Register Address Offset	Bit Fields
`siliconid1` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`id` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rev` `RO 0x1`
`siliconid2` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsv` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsv` `RO 0x0`
`wddbg` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`mode_1` `RW 0x3`		`mode_0` `RW 0x3`
`bootinfo` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`						`pincsel` `RO 0x0`		`pinbsel` `RO 0x0`			`csel` `RO 0x0`		`bsel` `RO 0x0`
`hpsinfo` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`can` `RO 0x0`	`dualcore` `RO 0x0`
`parityinj` `0x1C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`btac_1` `RW 0x0`	`btac_0` `RW 0x0`	`ghb_1` `RW 0x0`	`ghb_0` `RW 0x0`	`ictag_1` `RW 0x0`	`ictag_0` `RW 0x0`	`icdata_1` `RW 0x0`	`icdata_0` `RW 0x0`	`maintlb_1` `RW 0x0`	`maintlb_0` `RW 0x0`	`dcouter_1` `RW 0x0`	`dcouter_0` `RW 0x0`	`dctag_1` `RW 0x0`	`dctag_0` `RW 0x0`	`dcdata_1` `RW 0x0`	`dcdata_0` `RW 0x0`
`FPGA Interface Group`
`gbl` `0x20`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`intf` `RW 0x1`
`indiv` `0x24`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`crosstrigintf` `RW 0x1`	`stmeventintf` `RW 0x1`	`Reserved`	`traceintf` `RW 0x1`	`bscanintf` `RW 0x1`	`configiointf` `RW 0x1`	`jtagenintf` `RW 0x1`	`rstreqintf` `RW 0x1`
`module` `0x28`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`sdmmc` `RW 0x0`	`Reserved`	`emac_1` `RW 0x0`	`emac_0` `RW 0x0`	`spim_1` `RW 0x0`	`spim_0` `RW 0x0`
`Scan Manager Group`
`ctrl` `0x30`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`fpgajtagen` `RW 0x0`
`Freeze Control Group`
`vioctrl` `0x40`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`slew` `RW 0x0`	`wkpullup` `RW 0x0`	`tristate` `RW 0x0`	`bushold` `RW 0x0`	`cfg` `RW 0x0`
`hioctrl` `0x50`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`oct_cfgen_calstart` `RW 0x0`	`regrst` `RW 0x1`	`octrst` `RW 0x1`	`dllrst` `RW 0x1`	`slew` `RW 0x0`	`wkpullup` `RW 0x0`	`tristate` `RW 0x0`	`bushold` `RW 0x0`	`cfg` `RW 0x0`
`src` `0x54`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`vio1` `RW 0x0`
`hwctrl` `0x58`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`vio1state` `RO 0x2`		`vio1req` `RW 0x1`
`EMAC Group`
`ctrl` `0x60`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`										`ptpclksel_1` `RW 0x0`	`ptpclksel_0` `RW 0x0`	`physel_1` `RW 0x2`		`physel_0` `RW 0x2`
`l3master` `0x64`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`awcache_1` `RW 0x0`				`awcache_0` `RW 0x0`				`arcache_1` `RW 0x0`				`arcache_0` `RW 0x0`
`DMA Controller Group`
`ctrl` `0x70`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`irqnonsecure` `RW 0x0`								`mgrnonsecure` `RW 0x0`	`chansel_3` `RW 0x0`	`chansel_2` `RW 0x0`	`chansel_1` `RW 0x0`	`chansel_0` `RW 0x0`
`persecurity` `0x74`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`nonsecure` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`nonsecure` `RW 0x0`
`Preloader (initial software) Group`
`handoff` `0x80`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RW 0x0`
`Boot ROM Code Register Group`
`ctrl` `0xC0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`warmrstcfgio` `RW 0x0`	`warmrstcfgpinmux` `RW 0x0`
`cpu1startaddr` `0xC4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RW 0x0`
`initswstate` `0xC8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RW 0x0`
`initswlastld` `0xCC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`index` `RW 0x0`
`bootromswstate` `0xD0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`value` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`value` `RW 0x0`
`Warm Boot from On-Chip RAM Group`
`enable` `0xE0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`magic` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`magic` `RW 0x0`
`datastart` `0xE4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`offset` `RW 0x0`
`length` `0xE8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`size` `RW 0x0`
`execution` `0xEC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`offset` `RW 0x0`
`crc` `0xF0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`expected` `RW 0xE763552A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`expected` `RW 0xE763552A`
`Boot ROM Hardware Register Group`
`ctrl` `0x100`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`ensfmdwru` `RW 0x1`	`waitstate` `RW 0x0`
`SDMMC Controller Group`
`ctrl` `0x108`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`fbclksel` `RW 0x0`	`smplsel` `RW 0x0`			`drvsel` `RW 0x0`
`l3master` `0x10C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`hprotcache_0` `RW 0x0`	`hprotbuff_0` `RW 0x0`	`hprotpriv_0` `RW 0x1`	`hprotdata_0` `RW 0x1`
`NAND Flash Controller Register Group`
`bootstrap` `0x110`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`tworowaddr` `RW 0x0`	`noloadb0p0` `RW 0x0`	`page512` `RW 0x0`	`noinit` `RW 0x0`
`l3master` `0x114`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`awcache_0` `RW 0x0`				`arcache_0` `RW 0x0`
`USB Controller Group`
`l3master` `0x118`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`hprotcache_1` `RW 0x0`	`hprotcache_0` `RW 0x0`	`hprotbuff_1` `RW 0x0`	`hprotbuff_0` `RW 0x0`	`hprotpriv_1` `RW 0x1`	`hprotpriv_0` `RW 0x1`	`hprotdata_1` `RW 0x1`	`hprotdata_0` `RW 0x1`
`ECC Management Register Group`
`l2` `0x140`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`													`injd` `RW 0x0`	`injs` `RW 0x0`	`en` `RW 0x0`
`ocram` `0x144`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`derr` `RW 0x0`	`serr` `RW 0x0`	`injd` `RW 0x0`	`injs` `RW 0x0`	`en` `RW 0x0`
`usb0` `0x148`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`derr` `RW 0x0`	`serr` `RW 0x0`	`injd` `RW 0x0`	`injs` `RW 0x0`	`en` `RW 0x0`
`usb1` `0x14C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`derr` `RW 0x0`	`serr` `RW 0x0`	`injd` `RW 0x0`	`injs` `RW 0x0`	`en` `RW 0x0`
`emac0` `0x150`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`rxfifoderr` `RW 0x0`	`rxfifoserr` `RW 0x0`	`txfifoderr` `RW 0x0`	`txfifoserr` `RW 0x0`	`rxfifoinjd` `RW 0x0`	`rxfifoinjs` `RW 0x0`	`txfifoinjd` `RW 0x0`	`txfifoinjs` `RW 0x0`	`en` `RW 0x0`
`emac1` `0x154`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`rxfifoderr` `RW 0x0`	`rxfifoserr` `RW 0x0`	`txfifoderr` `RW 0x0`	`txfifoserr` `RW 0x0`	`rxfifoinjd` `RW 0x0`	`rxfifoinjs` `RW 0x0`	`txfifoinjd` `RW 0x0`	`txfifoinjs` `RW 0x0`	`en` `RW 0x0`
`dma` `0x158`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`derr` `RW 0x0`	`serr` `RW 0x0`	`injd` `RW 0x0`	`injs` `RW 0x0`	`en` `RW 0x0`
`can0` `0x15C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`derr` `RW 0x0`	`serr` `RW 0x0`	`injd` `RW 0x0`	`injs` `RW 0x0`	`en` `RW 0x0`
`can1` `0x160`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`derr` `RW 0x0`	`serr` `RW 0x0`	`injd` `RW 0x0`	`injs` `RW 0x0`	`en` `RW 0x0`
`nand` `0x164`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`			`rdfifoderr` `RW 0x0`	`rdfifoserr` `RW 0x0`	`wrfifoderr` `RW 0x0`	`wrfifoserr` `RW 0x0`	`eccbufderr` `RW 0x0`	`eccbufserr` `RW 0x0`	`rdfifoinjd` `RW 0x0`	`rdfifoinjs` `RW 0x0`	`wrfifoinjd` `RW 0x0`	`wrfifoinjs` `RW 0x0`	`eccbufinjd` `RW 0x0`	`eccbufinjs` `RW 0x0`	`en` `RW 0x0`
`qspi` `0x168`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`derr` `RW 0x0`	`serr` `RW 0x0`	`injd` `RW 0x0`	`injs` `RW 0x0`	`en` `RW 0x0`
`sdmmc` `0x16C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`derrportb` `RW 0x0`	`serrportb` `RW 0x0`	`derrporta` `RW 0x0`	`serrporta` `RW 0x0`	`injdportb` `RW 0x0`	`injsportb` `RW 0x0`	`injdporta` `RW 0x0`	`injsporta` `RW 0x0`	`en` `RW 0x0`
`Pin Mux Control Group`
`EMACIO0` `0x400`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO1` `0x404`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO2` `0x408`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO3` `0x40C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO4` `0x410`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO5` `0x414`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO6` `0x418`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO7` `0x41C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO8` `0x420`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO9` `0x424`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO10` `0x428`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO11` `0x42C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO12` `0x430`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`EMACIO13` `0x434`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO0` `0x450`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO1` `0x454`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO2` `0x458`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO3` `0x45C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO4` `0x460`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO5` `0x464`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO6` `0x468`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO7` `0x46C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO8` `0x470`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO9` `0x474`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO10` `0x478`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`FLASHIO11` `0x47C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO0` `0x480`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO1` `0x484`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO2` `0x488`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO3` `0x48C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO4` `0x490`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO5` `0x494`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO6` `0x498`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO7` `0x49C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO8` `0x4A0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO9` `0x4A4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO10` `0x4A8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO11` `0x4AC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO12` `0x4B0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO13` `0x4B4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO14` `0x4B8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO15` `0x4BC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO16` `0x4C0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO17` `0x4C4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO18` `0x4C8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GENERALIO28` `0x4F0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`														`sel` `RW 0x0`
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`														`sel` `RW 0x0`
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`														`sel` `RW 0x0`
`MIXED1IO0` `0x500`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO1` `0x504`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO2` `0x508`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO3` `0x50C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO4` `0x510`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO5` `0x514`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO6` `0x518`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO7` `0x51C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO8` `0x520`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO9` `0x524`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO10` `0x528`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO11` `0x52C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO12` `0x530`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO13` `0x534`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO14` `0x538`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO15` `0x53C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO16` `0x540`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO17` `0x544`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO18` `0x548`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO19` `0x54C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO20` `0x550`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`MIXED1IO21` `0x554`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`sel` `RW 0x0`
`GPLINMUX48` `0x578`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX49` `0x57C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX50` `0x580`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX51` `0x584`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX52` `0x588`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX53` `0x58C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX54` `0x590`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX55` `0x594`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX56` `0x598`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX57` `0x59C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX58` `0x5A0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX59` `0x5A4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX60` `0x5A8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX61` `0x5AC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX62` `0x5B0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX63` `0x5B4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX64` `0x5B8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX65` `0x5BC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX66` `0x5C0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX67` `0x5C4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX68` `0x5C8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX69` `0x5CC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLINMUX70` `0x5D0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX0` `0x5D4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX1` `0x5D8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX2` `0x5DC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX3` `0x5E0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX4` `0x5E4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX5` `0x5E8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX6` `0x5EC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX7` `0x5F0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX8` `0x5F4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX9` `0x5F8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX10` `0x5FC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX11` `0x600`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX12` `0x604`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX13` `0x608`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX14` `0x60C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX15` `0x610`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX16` `0x614`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX17` `0x618`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX18` `0x61C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX19` `0x620`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX20` `0x624`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX21` `0x628`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX22` `0x62C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX23` `0x630`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX24` `0x634`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX25` `0x638`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX26` `0x63C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX27` `0x640`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX28` `0x644`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX29` `0x648`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX30` `0x64C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX31` `0x650`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX32` `0x654`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX33` `0x658`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX34` `0x65C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX35` `0x660`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX36` `0x664`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX37` `0x668`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX38` `0x66C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX39` `0x670`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX40` `0x674`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX41` `0x678`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX42` `0x67C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX43` `0x680`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX44` `0x684`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX45` `0x688`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX46` `0x68C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX47` `0x690`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX48` `0x694`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX49` `0x698`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX50` `0x69C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX51` `0x6A0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX52` `0x6A4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX53` `0x6A8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX54` `0x6AC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX55` `0x6B0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX56` `0x6B4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX57` `0x6B8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX58` `0x6BC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX59` `0x6C0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX60` `0x6C4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX61` `0x6C8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX62` `0x6CC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX63` `0x6D0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX64` `0x6D4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX65` `0x6D8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX66` `0x6DC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX67` `0x6E0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX68` `0x6E4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX69` `0x6E8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`GPLMUX70` `0x6EC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`UART0USEFPGA` `0x6F4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`RGMII1USEFPGA` `0x6F8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`SPIS0USEFPGA` `0x6FC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`CAN0USEFPGA` `0x700`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`I2C0USEFPGA` `0x704`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`SDMMCUSEFPGA` `0x708`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`QSPIUSEFPGA` `0x70C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`SPIS1USEFPGA` `0x710`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`RGMII0USEFPGA` `0x714`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`UART1USEFPGA` `0x718`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`CAN1USEFPGA` `0x71C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`I2C3USEFPGA` `0x724`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`I2C2USEFPGA` `0x728`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`I2C1USEFPGA` `0x72C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`SPIM1USEFPGA` `0x730`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`
`SPIM0USEFPGA` `0x738`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`sel` `RW 0x0`