indiv

Used to disable individual interfaces between the FPGA and HPS.
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD08024

Offset: 0x24

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

crosstrigintf

RW 0x1

stmeventintf

RW 0x1

Reserved

traceintf

RW 0x1

bscanintf

RW 0x1

configiointf

RW 0x1

jtagenintf

RW 0x1

rstreqintf

RW 0x1

indiv Fields

Bit Name Description Access Reset
7 crosstrigintf

Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note that this doesn't prevent the HPS debug logic from sending triggers to the FPGA Fabric.

Value Description
0x0 FPGA Fabric cannot send triggers.
0x1 FPGA Fabric can send triggers.
RW 0x1
6 stmeventintf

Used to disable the STM event interface. This interface allows logic in the FPGA fabric to trigger events to the STM debug module in the HPS.

Value Description
0x0 STM event interface is disabled. Logic in the FPGA fabric cannot trigger STM events.
0x1 STM event interface is enabled. Logic in the FPGA fabric can trigger STM events.
RW 0x1
4 traceintf

Used to disable the trace interface. This interface allows the HPS debug logic to send trace data to logic in the FPGA fabric.

Value Description
0x0 Trace interface is disabled. HPS debug logic cannot send trace data to the FPGA fabric.
0x1 Trace interface is enabled. Other registers in the HPS debug logic must be programmmed to actually send trace data to the FPGA fabric.
RW 0x1
3 bscanintf

Used to disable the boundary-scan interface. This interface allows the FPGA JTAG TAP controller to execute boundary-scan instructions such as SAMPLE/PRELOAD, EXTEST, and HIGHZ. The boundary-scan interface must be enabled before attempting to send the boundary-scan instructions to the FPGA JTAG TAP controller.

Value Description
0x0 Boundary-scan interface is disabled. Execution of boundary-scan instructions in the FPGA JTAG TAP controller is unsupported and produces undefined results.
0x1 Boundary-scan interface is enabled. Execution of the boundary-scan instructions in the FPGA JTAG TAP controller is supported.
RW 0x1
2 configiointf

Used to disable the CONFIG_IO interface. This interface allows the FPGA JTAG TAP controller to execute the CONFIG_IO instruction and configure all device I/Os (FPGA and HPS). This is typically done before executing boundary-scan instructions. The CONFIG_IO interface must be enabled before attempting to send the CONFIG_IO instruction to the FPGA JTAG TAP controller.

Value Description
0x0 CONFIG_IO interface is disabled. Execution of the CONFIG_IO instruction in the FPGA JTAG TAP controller is unsupported and produces undefined results.
0x1 CONFIG_IO interface is enabled. Execution of the CONFIG_IO instruction in the FPGA JTAG TAP controller is supported.
RW 0x1
1 jtagenintf

Used to disable the JTAG enable interface (the fpgajtagen bit in the ctrl register). This interface allows logic in the FPGA fabric to disable the HPS JTAG operation.

Value Description
0x0 Disables the fpgajtagen bit found in the ctrl register.
0x1 Enables the fpgajtagen bit found in the ctrl register.
RW 0x1
0 rstreqintf

Used to disable the reset request interface. This interface allows logic in the FPGA fabric to request HPS resets. This field disables the following reset request signals from the FPGA fabric to HPS:[list][*]f2h_cold_rst_req_n - Triggers a cold reset of the HPS[*]f2h_warm_rst_req_n - Triggers a warm reset of the HPS[*]f2h_dbg_rst_req_n - Triggers a debug reset of the HPS[/list]

Value Description
0x0 Reset request interface is disabled. Logic in the FPGA fabric cannot reset the HPS.
0x1 Reset request interface is enabled. Logic in the FPGA fabric can reset the HPS.
RW 0x1