l2

This register is used to enable ECC on the L2 Data RAM. ECC errors can be injected into the write path using bits in this register. This register is reset by a cold reset (ignores warm reset). The interrupt status of the L2 ECC single/double bit error is handled in the General Interrupt Controller (GIC).

Module Instance	Base Address	Register Address
`sysmgr`	`0xFFD08000`	`0xFFD08140`

Offset: 0x140

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`													`injd` `RW 0x0`	`injs` `RW 0x0`	`en` `RW 0x0`

l2 Fields

Bit	Name	Description	Access	Reset
2	`injd`	Changing this bit from zero to one injects a double, non-correctable error into the L2 Data RAM. This only injects one double bit error into the L2 Data RAM.	`RW`	`0x0`
1	`injs`	Changing this bit from zero to one injects a single, correctable error into the L2 Data RAM. This only injects one error into the L2 Data RAM.	`RW`	`0x0`
0	`en`	Enable ECC for L2 Data RAM	`RW`	`0x0`