SDMMC Controller Group Register Descriptions Registers related to SDMMC Controller which aren't located inside the SDMMC itself. Offset: 0x108 ctrl Registers used by the SDMMC Controller. All fields are reset by a cold or warm reset. l3master Controls the L3 master HPROT AHB-Lite signal. These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation All fields are reset by a cold or warm reset.