EMAC Group Register Descriptions External control registers for the EMACs Offset: 0x60 ctrl Registers used by the EMACs. All fields are reset by a cold or warm reset. l3master Controls the L3 master ARCACHE and AWCACHE AXI signals. These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation All fields are reset by a cold or warm reset.