gbl

Used to disable all interfaces between the FPGA and HPS.
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD08020

Offset: 0x20

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

intf

RW 0x1

gbl Fields

Bit Name Description Access Reset
0 intf

Used to disable all interfaces between the FPGA and HPS. Software must ensure that all interfaces between the FPGA and HPS are inactive before disabling them.

Value Description
0x0 All interfaces between FPGA and HPS are disabled.
0x1 Interfaces between FPGA and HPS are not all disabled. Interfaces can be indivdually disabled by putting the HPS module associated with the interface in reset using registers in the Reset Manager or by using registers in this register group of the System Manager for interfaces without an associated module.
RW 0x1