src

Contains register field to choose between software state machine (vioctrl array index [1] register) or hardware state machine in the Freeze Controller as the freeze signal source for VIO channel 1. All fields are only reset by a cold reset (ignore warm reset).
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD08054

Offset: 0x54

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

vio1

RW 0x0

src Fields

Bit Name Description Access Reset
0 vio1

The freeze signal source for VIO channel 1 (VIO bank 2 and bank 3).

Value Description
0x0 VIO1 freeze signals are driven by software writing to the VIOCTRL[1] register. The VIO1-related fields in the hwctrl register are active but don't effect the VIO1 freeze signals.
0x1 VIO1 freeze signals are driven by the hardware state machine in the Freeze Controller. The VIO1-related fields in the hwctrl register are active and effect the VIO1 freeze signals.
RW 0x0