l3master

Controls the L3 master ARCACHE and AWCACHE AXI signals. These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation All fields are reset by a cold or warm reset.
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD08064

Offset: 0x64

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

awcache_1

RW 0x0

awcache_0

RW 0x0

arcache_1

RW 0x0

arcache_0

RW 0x0

l3master Fields

Bit Name Description Access Reset
15:12 awcache_1

Specifies the values of the 2 EMAC AWCACHE signals. The field array index corresponds to the EMAC index.

Value Description
0x0 Noncacheable and nonbufferable.
0x1 Bufferable only.
0x2 Cacheable, but do not allocate.
0x3 Cacheable and bufferable, but do not allocate.
0x4 Reserved.
0x5 Reserved.
0x6 Cacheable write-through, allocate on reads only.
0x7 Cacheable write-back, allocate on reads only.
0x8 Reserved.
0x9 Reserved.
0xa Cacheable write-through, allocate on writes only.
0xb Cacheable write-back, allocate on writes only.
0xc Reserved.
0xd Reserved.
0xe Cacheable write-through, allocate on both reads and writes.
0xf Cacheable write-back, allocate on both reads and writes.
RW 0x0
11:8 awcache_0

Specifies the values of the 2 EMAC AWCACHE signals. The field array index corresponds to the EMAC index.

Value Description
0x0 Noncacheable and nonbufferable.
0x1 Bufferable only.
0x2 Cacheable, but do not allocate.
0x3 Cacheable and bufferable, but do not allocate.
0x4 Reserved.
0x5 Reserved.
0x6 Cacheable write-through, allocate on reads only.
0x7 Cacheable write-back, allocate on reads only.
0x8 Reserved.
0x9 Reserved.
0xa Cacheable write-through, allocate on writes only.
0xb Cacheable write-back, allocate on writes only.
0xc Reserved.
0xd Reserved.
0xe Cacheable write-through, allocate on both reads and writes.
0xf Cacheable write-back, allocate on both reads and writes.
RW 0x0
7:4 arcache_1

Specifies the values of the 2 EMAC ARCACHE signals. The field array index corresponds to the EMAC index.

Value Description
0x0 Noncacheable and nonbufferable.
0x1 Bufferable only.
0x2 Cacheable, but do not allocate.
0x3 Cacheable and bufferable, but do not allocate.
0x4 Reserved.
0x5 Reserved.
0x6 Cacheable write-through, allocate on reads only.
0x7 Cacheable write-back, allocate on reads only.
0x8 Reserved.
0x9 Reserved.
0xa Cacheable write-through, allocate on writes only.
0xb Cacheable write-back, allocate on writes only.
0xc Reserved.
0xd Reserved.
0xe Cacheable write-through, allocate on both reads and writes.
0xf Cacheable write-back, allocate on both reads and writes.
RW 0x0
3:0 arcache_0

Specifies the values of the 2 EMAC ARCACHE signals. The field array index corresponds to the EMAC index.

Value Description
0x0 Noncacheable and nonbufferable.
0x1 Bufferable only.
0x2 Cacheable, but do not allocate.
0x3 Cacheable and bufferable, but do not allocate.
0x4 Reserved.
0x5 Reserved.
0x6 Cacheable write-through, allocate on reads only.
0x7 Cacheable write-back, allocate on reads only.
0x8 Reserved.
0x9 Reserved.
0xa Cacheable write-through, allocate on writes only.
0xb Cacheable write-back, allocate on writes only.
0xc Reserved.
0xd Reserved.
0xe Cacheable write-through, allocate on both reads and writes.
0xf Cacheable write-back, allocate on both reads and writes.
RW 0x0