GENERALIO28
This register is used to control the peripherals connected to spis0_clk
Only reset by a cold reset (ignores warm reset).
NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.
| Module Instance | Base Address | Register Address |
|---|---|---|
| sysmgr | 0xFFD08000 | 0xFFD084F0 |
Offset: 0x4F0
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
sel RW 0x0 |
||||||||||||||
GENERALIO28 Fields
| Bit | Name | Description | Access | Reset | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1:0 | sel | Select peripheral
signals connected spis0_clk.
|
RW | 0x0 |