FPGA Interface Group Register Descriptions
Registers used to enable/disable interfaces between the FPGA and HPS.
Required for either of the following situations:
(1)
Interfaces that cannot be disabled by putting an HPS module
associated with the interface into
reset; or (2)
HPS
modules that accept signals from the FPGA fabric and those signals might interfere
with the normal operation of the
module.
All registers are only reset by a cold reset (ignore warm reset).
Offset: 0x20