ctrl

Registers used by the SDMMC Controller. All fields are reset by a cold or warm reset.
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD08108

Offset: 0x108

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

fbclksel

RW 0x0

smplsel

RW 0x0

drvsel

RW 0x0

ctrl Fields

Bit Name Description Access Reset
6 fbclksel

Select which fb_clk to be used as cclk_in_sample. If 0, cclk_in_sample is driven by internal phase shifted cclk_in. If 1, cclk_in_sample is driven by fb_clk_in. No phase shifting is provided internally on cclk_in_sample. Note: Using the feedback clock (setting this bit to 1) is not a supported use model.

 RW 0x0
5:3 smplsel

Select which phase shift of the clock for cclk_in_sample. Note that the boot ROM programs this field to 0x0.

Value Description
0x0 0 degrees phase shifted clock is selected
0x1 45 degrees phase shifted clock is selected
0x2 90 degrees phase shifted clock is selected
0x3 135 degrees phase shifted clock is selected
0x4 180 degrees phase shifted clock is selected
0x5 225 degrees phase shifted clock is selected
0x6 270 degrees phase shifted clock is selected
0x7 315 degrees phase shifted clock is selected
RW 0x0
2:0 drvsel

Select which phase shift of the clock for cclk_in_drv. Note that the boot ROM programs this field to 0x3.

Value Description
0x0 Reserved
0x1 45 degrees phase shifted clock is selected
0x2 90 degrees phase shifted clock is selected
0x3 135 degrees phase shifted clock is selected
0x4 180 degrees phase shifted clock is selected
0x5 225 degrees phase shifted clock is selected
0x6 270 degrees phase shifted clock is selected
0x7 315 degrees phase shifted clock is selected
RW 0x0