emac0

This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset).

Module Instance	Base Address	Register Address
`sysmgr`	`0xFFD08000`	`0xFFD08150`

Offset: 0x150

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`rxfifoderr` `RW 0x0`	`rxfifoserr` `RW 0x0`	`txfifoderr` `RW 0x0`	`txfifoserr` `RW 0x0`	`rxfifoinjd` `RW 0x0`	`rxfifoinjs` `RW 0x0`	`txfifoinjd` `RW 0x0`	`txfifoinjs` `RW 0x0`	`en` `RW 0x0`

emac0 Fields

Bit	Name	Description	Access	Reset
8	`rxfifoderr`	This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC double bit, non-correctable error. It is set by hardware when double bit, non-correctable error occurs in EMAC0 RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
7	`rxfifoserr`	This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in EMAC0 RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
6	`txfifoderr`	This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC double bit, non-correctable error. It is set by hardware when double bit, non-correctable error occurs in EMAC0 TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
5	`txfifoserr`	This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in EMAC0 TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
4	`rxfifoinjd`	Changing this bit from zero to one injects a double, non-correctable error into the EMAC0 RXFIFO RAM. This only injects one double bit error into the EMAC0 RXFIFO RAM.	`RW`	`0x0`
3	`rxfifoinjs`	Changing this bit from zero to one injects a single, correctable error into the EMAC0 RXFIFO RAM. This only injects one error into the EMAC0 RXFIFO RAM.	`RW`	`0x0`
2	`txfifoinjd`	Changing this bit from zero to one injects a double, non-correctable error into the EMAC0 TXFIFO RAM. This only injects one double bit error into the EMAC0 TXFIFO RAM.	`RW`	`0x0`
1	`txfifoinjs`	Changing this bit from zero to one injects a single, correctable error into the EMAC0 TXFIFO RAM. This only injects one error into the EMAC0 TXFIFO RAM.	`RW`	`0x0`
0	`en`	Enable ECC for EMAC0 RAM	`RW`	`0x0`